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Author: Admin | 2025-04-27
In UVM. Normally the higher level component sets up configuration data base with handles and the lower level components do get them using get/set methods.37. What is the recommended way of assigning virtual interfaces to different components in a UVM verification methodology?The top-level testbench module which instantiates the DUT and interfaces will set the virtual interface in the uvm_config_db. A test class or any other component in the UVM component hierarchy can then query the uvm_config_db using the get() method to get handles to this virtual interface and use them for accessing signals. The following shows an example of how this is done. The module test actually instantiates a DUT and physical interface for an APB bus master. It then sets the virtual interface handle to the uvm_config_db.module test;logic pclk;logic [31:0] paddr;//Instantiate an APB bus master DUTapb_master apb_master(.pclk(pclk),*);//Instantiate a physical interface for APB interfaceapb_if apb_if(.pclk(pclk), *);initial begin//Pass this physical interface to test class top//which will further pass it down to env->agent->drv/sqr/monuvm_config_db#(virtual apb_if)::set(null, “uvm_test_top”, “vif”, apb_if);endendmoduleFollowing shows a APB Env class that uses the get() method in uvm_config_db toretrieve the virtual interface that was set in the top level test module.class apb_env extends uvm_env;`uvm_component_utils(apb_env);//ENV class will have agent as its sub componentapb_agent agt;//virtual interface for APB interfacevirtual apb_if vif;//Build phase - Construct agent and get virtual interface handle from test andpass it down to agentfunction void build_phase(uvm_phase phase);agt = apb_agent::type_id::create(“agt”, this);if (!uvm_config_db#(virtual apb_if)::get(this, ””, “vif”, vif))begin`uvm_fatal(“config_db_err”, “No virtual interface specified for this env instance”)enduvm_config_db#(virtual apb_if)::set( this, “agt”, “vif”, vif);endfunction: build_phaseendclass : apb_env38. Explain how simulation ends in UVM methodology?UVM has a phased execution which consists of a set of build phases, run phases and check phases. The run() phase is where the actual test simulation happens and during this phase every component can raise an objection in beginning and hold it until it is done with its activity. Once all components drops the objection, the run() phase completes and then check() phase of all components execute and then the test ends.This is how a normal simulation ends, but there are also controls on simulation timeouts to terminate the run() phase if
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