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Author: Admin | 2025-04-28
Sim help You have to take care of many things during gate sims run.1. If you are using same RTL simulation verification enviroment for gate sims then you have to put some delay while driving the inputs as here setup and hold come in picture.Why? The same exact stimulus should work in both RTL and gate sim (with or without timing). If you're driving the stimulus onto a synchronous I/F, there's no way you can violate setup/hold time. If you're driving the stimulus onto an asynchronous I/F, then you already take care of that problem by disabling the timing checks on those synchronizers (step 3).2. You have to initialize all uninitialized fllops.Why? Assuming all the necessary initialization of the chip is done correctly in the RTL simulation, you shouldn't have to do anything for the gate sim. Who cares if you have some uninitialized fllops in the netlist if they don't cause any problems.3. Disable the timing checks of all sync flops.Agree.4. Initialize all memory and registers of DUT just before DUT comes out of reset.This step doesn't even make sense. How can you initialize memories and registers when the chip is in reset? By using backdoor method? Again, the initialization routine that you use for the RTL should work for your gate sim. Please see my comment above.So what I'm trying to say is this. The only thing you need to do for gate sim (with timing) is disable timing checks on your synchronizers, unless you want to change your stimulus (NOOOOOOO). - Hung #5 Joined May 5, 2008 Messages 968 Helped 81 Reputation 164 Reaction score 57 Trophy points 1,308 Location Shang Hai Activity points 4,679 Re: gate level sim helpyes, you run the GLS should include some items: inilize some register, inilize some memory and close some timing check for corss-clock domain signals. #6 Joined May 15, 2007 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,503 Re: gate level sim helphi, once i start asserting/deasserting the reset i get a few timing violations .Should i consider this at all as valid violations?Also after these messages ,the devsel doesn't get asserted by the dut.Here pci interface is used.I really don't know how to go further with this.Meaning what are the various ways to debug issues in GLS.Thanks! #7 Joined Mar 31, 2006 Messages 30 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,288 Activity points 1,395 gate level sim helpwhy Disable the timing checks of all sync flops?asyn? #8 Joined May 15, 2007 Messages 36 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,503 Re: gate level sim helphi, My testbench is driving a signal Y
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