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Author: Admin | 2025-04-28
(synthesized, planned, placed, routed, retimed, final)synthesized : synthesis netlist. No placement has taken place at this stage.planned : Netlist after IO placement. No core logic has placed at this stage.placed : Netlist after full placement. Placement has occurred but no routing or retiming into Hyper registers has taken place at this stage. Simulation netlist will contain all netlist optimizations that occurred during placement.routed : Netlist after router stage. Full placement and routing has taken place however retiming of registers into Hyper register locations has not taken place yet. Simulation netlist will contain all netlist optimizations that occurred during placement and routing.retimed : Netlist after retime stage. Full placement, routing and retiming has taken place including retiming of registers into Hyper register locations. Simulation netlist will contain all netlist optimizations including hyper retiming that occurred during placement, routing & retiming.final : Netlist after final stage. Simulation netlist will contain all optimizations that occurred in any of the previous compilation steps. Main difference between this and the retimed netlist is that certain Hyper register locations can change due to hold time optimization.4) Generate the Gate-Level simulation netlist using the “quartus_eda” command.Run the following command to generate the appropriate gate-level simulation netlist:quartus_eda --simulation --snapshot= --partition=EG:quartus_eda --simulation Project_Top --snapshot=synthesized --partition=my_partitionOR:quartus_eda --simulation Project_Top --snapshot=final --partition=my_partitionThese commands will write out the simulation netlist (.vo or .vho) in the location specified in the “output directory” EDA Tool setting which defaults to “simulation/” (See EDA Tool Settings).5) Modify your testbench to account for any port list changes.The majority of the sub-block port list will be identical between the original RTL and the generated gate-level simulation netlist however there may be some constructs such as generics that get evaluated/removed and are not passed down through the gate-level port list.For this reason, you need to ensure that the parameterization of
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